chipflow.packaging.pins ======================= .. py:module:: chipflow.packaging.pins .. autoapi-nested-parse:: Pin dataclasses and types for package definitions. This module contains the fundamental building blocks for defining physical pin assignments and power/signal groupings in IC packages. Classes ------- .. autoapisummary:: chipflow.packaging.pins.PowerType chipflow.packaging.pins.JTAGWire chipflow.packaging.pins.PortType chipflow.packaging.pins.PowerPins chipflow.packaging.pins.JTAGPins chipflow.packaging.pins.BringupPins Module Contents --------------- .. py:class:: PowerType Bases: :py:obj:`enum.StrEnum` Type of power pin (power or ground) .. py:class:: JTAGWire Bases: :py:obj:`enum.StrEnum` Wire names in a JTAG interface .. py:class:: PortType Bases: :py:obj:`enum.StrEnum` Type of port .. py:class:: PowerPins Bases: :py:obj:`Generic`\ [\ :py:obj:`Pin`\ ] A matched pair of power pins, with optional notation of the voltage range. Attributes: power: The power (VDD) pin ground: The ground (VSS) pin voltage: Optional voltage range or specific voltage name: Optional name for this power domain .. py:method:: to_set() Convert power pins to a set .. py:class:: JTAGPins Bases: :py:obj:`Generic`\ [\ :py:obj:`Pin`\ ] Pins for a JTAG interface. Attributes: trst: Test Reset pin tck: Test Clock pin tms: Test Mode Select pin tdi: Test Data In pin tdo: Test Data Out pin .. py:method:: to_set() Convert JTAG pins to a set .. py:class:: BringupPins Bases: :py:obj:`Generic`\ [\ :py:obj:`Pin`\ ] Essential pins for bringing up an IC, always in fixed locations. These pins are used for initial testing and debug of the IC. Attributes: core_power: List of core power pin pairs core_clock: Core clock input pin core_reset: Core reset input pin core_heartbeat: Heartbeat output pin (for liveness testing) core_jtag: Optional JTAG interface pins .. py:method:: to_set() Convert all bringup pins to a set