Wishbone bus

Warning

This manual is a work in progress and is seriously incomplete!

The amaranth_soc.wishbone.bus module provides Wishbone bus primitives.

class amaranth_soc.wishbone.bus.CycleType

Wishbone Registered Feedback cycle type.

CLASSIC = 0
CONST_BURST = 1
INCR_BURST = 2
END_OF_BURST = 7
class amaranth_soc.wishbone.bus.BurstTypeExt

Wishbone Registered Feedback burst type extension.

LINEAR = 0
WRAP_4 = 1
WRAP_8 = 2
WRAP_16 = 3
class amaranth_soc.wishbone.bus.Feature

Optional Wishbone interface signals.

ERR = 'err'
RTY = 'rty'
STALL = 'stall'
LOCK = 'lock'
CTI = 'cti'
BTE = 'bte'
class amaranth_soc.wishbone.bus.Signature

Wishbone interface signature.

See the Wishbone specification for description of the Wishbone signals. The RST_I and CLK_I signals are provided as a part of the clock domain that drives the interface.

Parameters:

  • addr_width (int) – Width of the address signal.

  • data_width (8, 16, 32 or 64) – Width of the data signals (“port size” in Wishbone terminology).

  • granularity (8, 16, 32, 64 or None) – Granularity of select signals (“port granularity” in Wishbone terminology). Optional. If None (by default), the granularity is equal to data_width.

  • features (iter(Feature)) – Selects additional signals that will be a part of this interface. Optional.

  • attributes (Interface)

  • --------------------

  • depending (The correspondence between the Amaranth-SoC signals and the Wishbone signals changes)

  • target. (on whether the interface acts as an initiator or a)

  • adr (Signal(addr_width)) – Corresponds to Wishbone signal ADR_O (initiator) or ADR_I (target).

  • dat_w (Signal(data_width)) – Corresponds to Wishbone signal DAT_O (initiator) or DAT_I (target).

  • dat_r (Signal(data_width)) – Corresponds to Wishbone signal DAT_I (initiator) or DAT_O (target).

  • sel (Signal(data_width // granularity)) – Corresponds to Wishbone signal SEL_O (initiator) or SEL_I (target).

  • cyc (Signal()) – Corresponds to Wishbone signal CYC_O (initiator) or CYC_I (target).

  • stb (Signal()) – Corresponds to Wishbone signal STB_O (initiator) or STB_I (target).

  • we (Signal()) – Corresponds to Wishbone signal WE_O (initiator) or WE_I (target).

  • ack (Signal()) – Corresponds to Wishbone signal ACK_I (initiator) or ACK_O (target).

  • err (Signal()) – Optional. Corresponds to Wishbone signal ERR_I (initiator) or ERR_O (target).

  • rty (Signal()) – Optional. Corresponds to Wishbone signal RTY_I (initiator) or RTY_O (target).

  • stall (Signal()) – Optional. Corresponds to Wishbone signal STALL_I (initiator) or STALL_O (target).

  • lock (Signal()) – Optional. Corresponds to Wishbone signal LOCK_O (initiator) or LOCK_I (target). Amaranth-SoC Wishbone support assumes that initiators that don’t want bus arbitration to happen in between two transactions need to use lock feature to guarantee this. An initiator without the lock feature may be arbitrated in between two transactions even if cyc is kept high.

  • cti (Signal()) – Optional. Corresponds to Wishbone signal CTI_O (initiator) or CTI_I (target).

  • bte (Signal()) – Optional. Corresponds to Wishbone signal BTE_O (initiator) or BTE_I (target).

addr_width
data_width
granularity
features
create(*, path=None, src_loc_at=0)

Create a compatible interface.

See wiring.Signature.create() for details.

Return type:

An Interface object using this signature.

__eq__(other)

Compare signatures.

Two signatures are equal if they have the same address width, data width, granularity and features.

class amaranth_soc.wishbone.bus.Interface

Wishbone bus interface.

Note that the data width of the underlying memory map of the interface is equal to port granularity, not port size. If port granularity is less than port size, then the address width of the underlying memory map is extended to reflect that.

Parameters:

  • addr_width (int) – Width of the address signal. See Signature.

  • data_width (int) – Width of the data signals. See Signature.

  • granularity (int) – Granularity of select signals. Optional. See Signature.

  • features (iter(Feature)) – Describes additional signals of this interface. Optional. See Signature.

  • path (iter(str)) – Path to this Wishbone interface. Optional. See wiring.PureInterface.

Attributes:

memory_map (MemoryMap) – Memory map of the bus. Optional.

addr_width
data_width
granularity
features
memory_map
class amaranth_soc.wishbone.bus.Decoder

Wishbone bus decoder.

An address decoder for subordinate Wishbone buses.

Parameters:

  • addr_width (int) – Address width. See Signature.

  • data_width (int) – Data width. See Signature.

  • granularity (int) – Granularity. See Signature

  • features (iter(Feature)) – Optional signal set. See Signature.

  • alignment (int, power-of-2 exponent) – Window alignment. Optional. See memory.MemoryMap.

Attributes:

bus (Interface) – Wishbone bus providing access to subordinate buses.

align_to(alignment)

Align the implicit address of the next window.

See MemoryMap.align_to() for details.

add(sub_bus, *, name=None, addr=None, sparse=False)

Add a window to a subordinate bus.

The decoder can perform either sparse or dense address translation. If dense address translation is used (the default), the subordinate bus must have the same data width as the decoder; the window will be contiguous. If sparse address translation is used, the subordinate bus may have data width less than the data width of the decoder; the window may be discontiguous. In either case, the granularity of the subordinate bus must be equal to or less than the granularity of the decoder.

See MemoryMap.add_resource() for details.

class amaranth_soc.wishbone.bus.Arbiter

Wishbone bus arbiter.

A round-robin arbiter for initiators accessing a shared Wishbone bus.

Parameters:
Attributes:

bus (Interface) – Shared Wishbone bus.

add(intr_bus)

Add an initiator bus to the arbiter.

The initiator bus must have the same address width and data width as the arbiter. The granularity of the initiator bus must be greater than or equal to the granularity of the arbiter.