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ChipFlow Platform Documentation
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ChipFlow Platform Documentation

Getting Started

  • Chip Configurator
  • Getting Started with ChipFlow
  • Introduction to the ChipFlow platform

Examples

  • ChipFlow Examples
    • Getting Started with ChipFlow Examples
    • Minimal SoC Example
    • MCU SoC Example

Reference

  • ChipFlow Library Documentation
    • Getting Started with ChipFlow
    • ChipFlow Architecture Overview
    • Simulation Guide
    • Intro to chipflow.toml
    • project_name
    • clock_domains
    • process
    • package
    • The chipflow command
    • Using Pin Signatures and Software Drivers
    • Platform API Reference
      • chipflow
        • chipflow.auth
        • chipflow.auth_command
        • chipflow.common
        • chipflow.config
          • chipflow.config.parser
        • chipflow.packages
        • chipflow.packaging
          • chipflow.packaging.allocation
          • chipflow.packaging.base
          • chipflow.packaging.commands
          • chipflow.packaging.grid_array
          • chipflow.packaging.lockfile
          • chipflow.packaging.openframe
          • chipflow.packaging.pins
          • chipflow.packaging.port_desc
          • chipflow.packaging.standard
          • chipflow.packaging.utils
        • chipflow.platform
          • chipflow.platform.base
          • chipflow.platform.io
            • chipflow.platform.io.annotate
            • chipflow.platform.io.iosignature
            • chipflow.platform.io.signatures
            • chipflow.platform.io.sky130
        • chipflow.utils
    • Pin Signature Architecture (Contributor Guide)
  • Digital IP Library
    • Base Peripherals
    • I/O Peripherals
    • Memory Peripherals
    • Processors
  • Indices and tables
  • Amaranth Language and Toolchain
    • Introduction
    • Installation
    • Getting started
    • Tutorial
    • Language guide
    • Language reference
    • Standard library
      • Enumerations
      • Data structures
      • Interfaces and connections
      • Interface metadata
      • Data streams
      • Memory arrays
      • Input/output buffers
      • Clock domain crossing
      • Code conversion
      • First-in first-out queues
      • Cyclic redundancy checks
        • Algorithm catalog
    • Simulator
    • Platform integration
      • Altera
      • Gowin
      • Lattice
      • Quicklogic
      • SiliconBlue
      • Xilinx
    • Changelog
    • Contributing
  • Amaranth System-on-a-Chip toolkit
    • Memory maps
    • Wishbone
      • Wishbone bus
    • CSR
      • CSR bus
      • CSR registers
      • CSR fields
    • GPIO
  • Support
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Digital IP Library

A curated collection of parameterised and configurable RTL cores implemented or wrapped with Amaranth along with metadata for use with the ChipFlow platform.

Contents:

  • Base Peripherals
  • I/O Peripherals
  • Memory Peripherals
  • Processors

Indices and tables

  • Index

  • Module Index

  • Search Page

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Base Peripherals
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Pin Signature Architecture (Contributor Guide)
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