chipflow.packaging.port_desc

Port description models for pin allocation.

This module provides models for describing port-to-pin mappings and managing the overall port map for an IC package.

Classes

PortDesc	Description of a port and its pin assignment.
PortMap	Mapping of components to interfaces to ports.

Module Contents

class chipflow.packaging.port_desc.PortDesc

Bases: pydantic.BaseModel, Generic[chipflow.packaging.pins.Pin]

Description of a port and its pin assignment.

Attributes:

type: Type of port (e.g., ‘io’, ‘clock’, ‘reset’, ‘power’, ‘heartbeat’) pins: List of pins assigned to this port, or None if not yet allocated port_name: Name of the port iomodel: IO model configuration for this port

property width

Width of the port (number of pins)

property direction

Direction of the port

property invert: collections.abc.Iterable[bool] | None

Inversion settings for port wires

Return type:

collections.abc.Iterable[bool] | None

class chipflow.packaging.port_desc.PortMap

Bases: pydantic.BaseModel

Mapping of components to interfaces to ports.

This represents the complete pin allocation for an IC package, organized hierarchically by component and interface.

get_ports(component, interface)

Get ports for a specific component and interface.

Args:

component: Component name interface: Interface name

Returns:

Dictionary of port names to PortDesc, or None if not found

Parameters:

• component (str)

• interface (str)

Return type:

Interface | None

get_clocks()

Get all clock ports in the port map

Return type:

List[PortDesc]

get_resets()

Get all reset ports in the port map

Return type:

List[PortDesc]